Juan Boon und Assignee - Info zur Person

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Low pre-heat pressure CVD TiN process - Chartered Semiconductor ...

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Tan, Juan Boon (Singapore, SG). Application Number: Assignee: Chartered Semiconductor Manufacturing Company (Singapore, SG). Primary Class:. › ...

Patents Assigned to Chartered Semiconductor Manufacturing ...

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Date of Patent: June 11, Assignee: Chartered Semiconductor Manufacturing Company. Inventors: Chim-Seng Seet, Chyi Shyuam Chern, Juan Boon Tan ... Date of Patent: July 6, Assignee: Chartered Semiconductor Manufacturing Ltd. Inventors: Xianbin Wang, Juan Boon Tan, Liang-Choo Hsia, Teck Jung Tang, ... › assignee

US B1 - Accurate wafer patterning method for mass production...

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Inventors, Juan Boon Tan, Tak Yan Tse, Sajan Marokkey Raphael, Fang Hong Gn. Original Assignee, Chartered Semiconductor Manufacturing Ltd.

US B2 - Structure and method for fabricating a bond pad...

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... Hsia Liang Choo, Lim Yeow Kheng, Alan Cuthbertson, Tan Juan Boon. Original Assignee, Chartered Semiconductor Manufacturing, Ltd.

INTEGRATED CIRCUIT SYSTEM EMPLOYING ALTERNATING CONDUCTIVE LAYERS -...

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Assignees: CHARTERED SEMICONDUCTOR MANUFACTURING LTD A method for manufacturing an integrated circuit system comprising:providing a substrate Patent applications by Juan Boon Tan, Singapore SG.

Implantation for shallow trench isolation (STI) formation and for...

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Assignees: CHARTERED SEMICONDUCTOR MANUFACTURING LTD [0028]It will be understood that the foregoing process is not limited to formation of dielectric Patent applications by Juan Boon Tan, Singapore SG.

U.S. Patent: Preserving the zero mark for wafer alignment...

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Inventors: Tan; Juan Boon (Singapore, SG); Yang; Zuo (Singapore, ... Assignee: Chartered Semiconductor Manufacturing, Ltd. (Singapore, SG).

RELIABLE INTERCONNECTS - Patent application

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Assignees: CHARTERED SEMICONDUCTOR MANUFACTURING LTD Patent applications by Juan Boon Tan, Singapore SG

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